EE Herald

AI EDA tools: AutoChip Leverages Large Language Models for Verilog Module Generation

A new tool, AI VLSI semiconductor design EDA tool AutoChip, has been developed to generate functional Verilog modules from initial design prompts and testbenches using large language models (LLMs).
Design-Reuse

AMIQ EDA Releases the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development, today ...
EDN

An overview of SystemVerilog 3.1

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along ...
EDN

How to implement DSP algorithms using the Xilinx Spartan-3E starter board

Editor's Note: This “How To” tutorial is an excerpt from a recently published book: Embedded Design Using Programmable Gate Arrays by Dennis Silage (ISBN-13: 978-1589094864). Dennis is a Professor in ...
Design-Reuse

Guidelines for Verilog-A Compact Model Coding

The Verilog-AMS hardware description language [1] includes extensions dedicated to compact modeling, but does not define a reserved subset for compact modeling. This lack of specification combined ...