GitHub

PyXHDL - Python Frontend For VHDL And Verilog

PyXHDL born for developers who are not really in love with any of the HDL languages and instead appreciate the simplicity and flexibility of using Python for their workflows. PyXHDL allows to write ...
IEEE

Generation of Synthesizable Verilog Code From Natural Language Specifications

Abstract: This study presents a method for generating synthesizable Verilog code for digital integrated circuits directly from natural-language specifications. The approach combines large language ...
IEEE

RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique

Abstract: The automatic generation of RTL code (e.g., Verilog) using natural language instructions and large language models (LLMs) has attracted significant research interest recently. However, most ...
Design-Reuse

Implementing C model integration using DPI in SystemVerilog

In the current era of machine learning and artificial intelligence, accelerator based SoCs have more complex processing of data and those circuits have software and design verification cycles. These ...
Hackaday

Logic Analyzers For FPGAs: A Verilog Odyssey

Sometimes you start something simple and then it just leads to a chain reaction of things. I wanted to write a post about doing state machines in Verilog and target the Lattice iCEstick board that we ...
GitHub

PicoRV32 - A Size-Optimized RISC-V CPU

PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt ...