Verific App Store Opens with Downloadable Examples of Parser Platform Applications

Initial offerings include a hierarchy explorer, linter, HDL editor, signal tracer, essential tools for hardware design and verificationVerific ...
GitHub

Datasets-and-Benchmarks.md

CalTennis: Large Multi-View Tennis Video Dataset and Benchmark of Monocular-to-3D Pose Estimation 2026-06-18 Show The Caltech Tennis Dataset (CalTennis) is a large-scale video benchmark for evaluating ...
IEEE

Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA

Abstract: SystemVerilog Assertions (SVAs) are critical for verifying the correctness of hardware designs, but manually writing them from natural language property descriptions, i.e., NL2SVA, remains a ...
Design-Reuse

Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach

In today’s fast-paced silicon industry, hardware design is under constant pressure to innovate, iterate, and ship faster. Traditional Register Transfer Level (RTL) design processes—though foundational ...
IEEE

RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models

Abstract: This paper presents RTLFixer, a novel framework enabling automatic syntax errors fixing for Verilog code with Large Language Models (LLMs). Despite LLM’s promising capabilities, our analysis ...
GitHub

ECE 27000 Verilog Simulator

If you're a student in ECE 27000 in the current semester, read this. It's likely that you may find example code in here that you may feel tempted to use in lab assignments for classes if you dig deep ...
Hacker

Top 4 HDL Simulators for Beginners

When learning to program FPGAs or ASICs using hardware description languages, such as Verilog or VHDL, being able to simulate code is an important part of the learning process. In fact, being able to ...