Most electronic memory storage devices require the ability to trap large numbers of electrons for each bit of memory. In an ...
SANTA CLARA, CALIFORNIA - JANUARY 22: The Intel logo is displayed on a sign in front of Intel headquarters on January 22, 2026 in Santa Clara, California. Intel will report fourth-quarter earnings ...
Huawei is touting a semiconductor advance - including something it calls the "Tau Scaling Law" as a successor to Moore's Law - but at least one chip expert says the news is more branding than ...
[Shanghai, China, May 25, 2026] Today, at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), He Tingbo from HUAWEI delivered a keynote speech titled "New Semiconductor Path in ...
Researchers from the University of California, Berkeley, along with Stanford collaborators, have successfully used a ferroelectric material to overcome a longstanding limitation in gallium nitride ...
Small, isolated power supplies provide power across isolation barriers in applications from electric vehicle traction inverters to factory control modules. In this Power Tip, I’ll examine different ...
In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize ...
Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even ...
Abstract: The low on-resistance of wide-band-gap (WBG) transistors is a key feature for efficient power converters; however, the anomalous loss in their output capacitance (COSS) severely limits their ...
Abstract: In recent years, the negative capacitance effect in ferroelectric (FE) materials has attracted significant attention from many researchers around the world. The negative capacitance effect ...