GitHub

Unclear interaction between address translation algorithm and translation cache, and potential infinite loop

The results of implicit address-translation reads in step 2 may be held in a read-only, incoherent address-translation cache but not shared with other harts. [ ... ] Entries in the address-translation ...
IEEE

Enhanced Cache Replacement Strategy for Named Data Networking: A Modified LeCaR Algorithm with Eviction History Tracking

Abstract: Efficient content retrieval in Named Data Networking (NDN) relies on optimized caching mechanisms. Traditional cache replacement policies, such as Least Recently Used (LRU) and Least ...
TechSpot

AMD patent proposes new memory module to double DDR5 speeds

The takeaway: AMD is exploring a new approach to system memory that could reshape the trajectory of DDR5, which has struggled to keep pace with the performance demands of gaming, artificial ...
GitHub

Explainer: Memory Cache Metrics API with Eviction Tracking

The Memory Cache Metrics API with Eviction Tracking addresses critical performance issues in containerized environments where memory pressure can cause cache thrashing, leading to degraded application ...
IEEE

Efficient GPU Memory Resource Scheduling Algorithm for Vehicle Detection Tasks in High Concurrent Scenarios

Abstract: In response to the fierce competition and low utilization of GPU memory resources in high concurrency vehicle detection tasks at electric vehicle charging stations, this paper proposes a ...