Semiconductor Engineering

Simplifying HW/SW Co-Verification With PSS Led UVM And C Tests

The complexity of system on chips (SoCs) continues to grow rapidly with the integration of more functionality onto a single chip. As a result, traditional verification methodologies struggle to keep ...
IEEE

Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator

Abstract: Real Number Modelling (RNM) has become more common as a part of mixed-signal SoC validation. The paper illustrates modelling Phase Locked Loops (PLL) using SystemVerilog-Real Number ...
Semiconductor Engineering

Debug This! How To Simplify Coverage Analysis And Closure

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based ...
Design-Reuse

Mentor Graphics Announces Veloce Strato Platform Scales Up to 15BG

WILSONVILLE, Ore., Feb. 16, 2017 – Mentor Graphics® Corporation (NASDAQ: MENT) today announced the Veloce® Strato™ emulation platform. The Veloce Strato platform is Mentor's third generation ...