Semiconductor Engineering

Largest High-Quality Verilog Dataset for LLM Fine-Tuning (Univ. of Florida)

A new technical paper titled “VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation” was published by researchers at the University of Florida.
IEEE

Improving LLM-Based Verilog Code Generation with Data Augmentation and RL

Abstract: Large language models (LLMs) have recently attracted significant attention for their potential in Verilog code generation. However, existing LLM-based methods face several challenges, ...
C&EN

Non-Volatile Reconfigurable Four-Mode van der Waals Transistors and Transformable Logic Circuits

Department of Electrical and Computer Engineering, University of Illinois at Urbana−Champaign, Urbana, Illinois 61801, United States ...
GitHub

waveform-analysis

Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design. Gate-level ...
GitHub

waveform-analysis

Gate-level implementation of a half-subtractor using Verilog, featuring a comprehensive testbench, truth table validation, and waveform analysis for beginners in digital design. Gate-level ...
IEEE

Design and application analysis of arithmetic logic unit in digital systems

Abstract: This article consists of five important parts. Introduction, fundamental theoretical analysis of Arithmetic Logic Unit (ALU), Verilog coding and simulation, the application of ALU, ...