Photonics is forcing EDA to verify not just chips, but the physics of light inside full electro-optical systems.

Recently, a technique called equality saturation adapted e-graphs for program optimization. Equality saturation can ...

Scaling NoCs across chiplets requires earlier validation of coherency, congestion, thermal effects, and fault behavior.

This repository contains the code and data for training a Verilog generation model using reinforcement learning (RL) with feedback from testbenches. The goal is to improve the quality of generated ...

A parameterised Verilog/VHDL line buffer for real-time image processing, packaged as a reusable AXI4-Stream IP core for Xilinx Zynq SoCs. The core is packaged as a custom IP block in Vivado IP ...

For forty years, the secret language that lets software talk to hardware was owned by a handful of companies. Then a free alternative escaped the lab—and turned chip design into a matter of statecraft ...