GitHub

Verilog Generation with Reinforcement Learning

This repository contains the code and data for training a Verilog generation model using reinforcement learning (RL) with feedback from testbenches. The goal is to improve the quality of generated ...
note

[Verilog] Does ignoring warnings cause data loss? The trap of implicit bit-width adjustment

A student who just started their job came to me with a pale face for advice. "In our real-device testing, a bug occasionally occurs where the calculation result becomes a completely different value.
GitHub

Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data

Chameleon is the first chip carrying out end-to-end FSL and CL with temporal data (no off-chip embedder, all weights on-chip), with three key innovations all validated in silicon: Chameleon builds on ...
Hacker

The Open Chip Revolution Has Reached the Real World

For forty years, the secret language that lets software talk to hardware was owned by a handful of companies. Then a free alternative escaped the lab—and turned chip design into a matter of statecraft ...
Communications of the ACM

egg: Fast and Extensible Equality Saturation

Recently, a technique called equality saturation adapted e-graphs for program optimization. Equality saturation can ...