GitHub

Asynchronous dual clock FIFO

This repository stores a verilog description of dual clock FIFO. A FIFO is a convenient circuit to exchange data between two clock domains. It manages the RAM addressing internally, the clock domain ...
GitHub

Bambu may generate wrong Verilog code.

Tool Version: https://release.bambuhls.eu/bambu-2024.10.AppImage OS Version: Ubuntu 22.04.5 Frontend Compiler Version: clang-14, gcc-11 Simulator: iverilog-13 First ...
IEEE

Verilog Code Generation of Hierarchical Design Using LLMs

Abstract: Creating RTL hierarchy and generating module-by-module Verilog code, both through a large language model (LLM), are presented. (1) For RTL hierarchy, LLM is prompted to identify a list of ...
IEEE

hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation

Abstract: Large language models (LLMs) are playing an increasingly large role in domains such as code generation, including hardware code generation, where Verilog is the key language. However, the ...