IEEE

A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip Technique With Background Offset Calibration

Abstract: This article presents a 7-bit, 1.15-GS/s, 2.6-bit/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that incorporates a comparator decision skip ...
IEEE

Multiuser-MIMO Systems Using Comparator Network-Aided Receivers With 1-Bit Quantization

Abstract: Low-resolution analog-to-digital converters (ADCs) are promising for reducing energy consumption and costs of multiuser multiple-input multiple-output (MIMO) systems with many antennas. We ...