Semiconductor Engineering

Universal Verification Methodology Running Out Of Steam

For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Design-Reuse

Silicon Interfaces announces the release of its IEEE 1394 uVC Verification IP using Cadence IPCM Universal Reuse Methodology (URM)

October 19, 2007 -- Silicon Interfaces' IEEE 1394-1995/2000 Link Layer Controller uVC is a fully documented, off the shelf component using Cadence Incisive Plan-to-Closure Universal Reuse Methodology ...