Asynchronous, or clockless, logic–an alternative to standard digital circuits that avoids many of their problems–is beginning to look attractive for embedded designs in consumer electronics and mobile ...

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...

The VITA46 VPX standarddefines a chassis that can accommodateall manner of cards with a commonform factor (Reference 1). Thecards plug into a common backplane.This design employs the VITA46.4standard ...

CMOS is, and will continue to be, the work-horse process technology of the semi-conductor industry. But designers of large devices, of complex SoCs and of devices using multiple IP elements are ...

You only need to validate one core of a CMP design. So if that core is simpler, validation is easier. And you have to worry about the rest of the logic no matter what your core design is. You dont get ...

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device operates with ...

Earlier designs were smaller, less complex, and had simpler clocking. A few years back, verification was much easier and clock modeling was not such a big concern. With the drastic increase in the use ...

In the simulation and verification world, particularly with regard to system-on-a-chip (SoC) design closure, certain fault types have made their way to silicon with greater frequency. Many of today's ...

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.

Pity the poor TTL computer aficionado. It’s an obsession, really — using discrete logic chips to scratch-build a computer that would probably compare unfavorably to an 80s era 8-bit machine in terms ...