EDN

“Do’s and Don’ts” when considering an FPGA to structured ASIC design methodology

More and more engineers are considering structured ASICs when they are designing advanced systems, because these components offer low unit cost, low power, and high performance along with fast ...
Design-Reuse

Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach

Geneva -- September 22,2008 - Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated ...
Design-Reuse

Open-Silicon Awarded Patent for Low Power ASIC Design Methodology

MILPITAS, Calif. – September 14, 2011 – Open-Silicon, Inc., a leading SoC design and semiconductor manufacturing company, announced today that the United States Patent and Trademark Office has ...
EDN

ASIC-Style Design Techniques for Programmable Devices

Advances in process technology are enabling a profound increase in the number of commercial applications for field programmable gate arrays (FPGAs). Technology breakthroughs from 10-million gate ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
Electronic Design

ASIC-Like FPGA Methodology Saves Up To $9,925,000 In NRE Costs

Not all companies have $10 million in their back pockets for the non-recurring expenses (NRE) today's ASIC design starts require. Fortunately, that kind of cash isn't necessary anymore, thanks to ...
Semiconductor Engineering

FPGA Design Tradeoffs Getting Tougher

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the ...